The present invention relates to a semiconductor device and more particularly to a technique which is useful for the semiconductor device having a package on package (POP) structure in which a plurality of semiconductor packages are stacked in a multistage manner.
As an aspect of a semiconductor package, a system in package (SIP) is known, in which a system is configured by mounting a plurality of semiconductor chips of different kinds (for example, a microcomputer chip and a memory chip) on a single wiring substrate.
As an example of the SIP of this kind, there is a multi chip module (MCM) described in Japanese patent laid-open No. 10-12809 (Patent Document 1). The MCM includes a multilayer wiring substrate having an insulating layer and a wiring layer and on the surface of the multilayer wiring substrate, a plurality of chips are mounted using a flip-chip method.
On the backside of the multilayer wiring substrate, a plurality of conductive pads for external input/output signals arranged in a grid pattern are formed, and an external input/output signal terminal including a solder ball etc. is coupled onto the pad. Further, on the surface and in the inner layer of the multilayer wiring substrate, signal wirings that couple the terminals of the plurality of chips and the external input/output signal terminals, and signal wirings that couple the terminals of the chips are formed.
Furthermore, within the conductive pad for external input/output signal arranged on the backside of the multilayer wiring substrate, a plurality of conductive terminals for inspection that couple the terminals of the chips and are not coupled to the outside is formed and it is possible to inspect the connection state of all the terminals of the chips and the operation of each chip by applying an inspection probe to the conductive terminal for inspection.
On the other hand, as a semiconductor package in an aspect different from that of the above SIP, there is a package on package (POP) described in Japanese patent laid-open No. 2007-123454 (Patent Document 2). The POP is a lamination package different from the SIP in which a plurality of chips are mounted on a single wiring substrate. In the POP, for example, a package including a wiring substrate mounting a microcomputer chip and a package including a wiring substrate mounting a memory chip are prepared and its system is configured by overlapping the packages to couple their chips to each other.
The POP includes a plurality of wiring substrates, and therefore, even when the number of input/output terminals of the microcomputer chips increases according to the performance level of the system, there is an advantage in that the number of signal wirings can be increased compared to that of the SIP with the same mounting area. In addition, in the POP, because the chips are coupled to each other after the chips are mounted on each wiring substrate, it is possible to determine the connection state of the chip and the wiring substrate prior to the process for coupling the chips to each other, which is effective to improve the yield during package assembly. Further, it is also possible to flexibly cope with a reduction or increase in the kinds of the systems compared to the SIP.